Accelerated scan circuitry and method for reducing scan test data volume and execution time
US7197681B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2004 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Dec 5, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.