Materials and method to seal vias in silicon substrates
US7199450B2 · kind B2 · utility
1Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 2005 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | May 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via at an elevated temperature. A supply chamber is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.