Chip package structure and process for fabricating the same
US7199479B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2005 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Apr 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package structure comprises a carrier, a chip and an underfill. The chip has an active surface on which a plurality of bumps are formed. The chip is flip-chip bonded onto the carrier with the active surface facing the carrier, and is electrically connected to the carrier through the bumps. The underfill is filled between the chip and the carrier. A portion of the underfill near the chip serves as a first underfill portion. The portion of the underfill near the carrier serves as a second underfill portion. The Young's modulus of the first underfill portion is smaller than the Young's modulus of the second underfill portion. The second underfill portion can be optionally replaced with a selected encapsulation. The selected encapsulation covers the chip and the carrier around the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.