Logic circuit arrangement

US7199618B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Jorg Gliese · Munich, DE
• Michael Scheppler · Gröbenzell, DE

Key dates

• Filing date: Nov 19, 2004
• Grant date: Apr 3, 2007
• Expiry date: Jun 29, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/1737
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A logic circuit arrangement including at least two data signal inputs, at which at least two data signals are provided, a first signal path coupled to the data signal inputs, and having a plurality of transistors of a first conduction type, and a plurality of control inputs coupled to the transistors.