Michael Scheppler
9Patents
4h-index
12Co-inventors
46Inventor score
Filing activity: Nov 19, 2004 → Jul 12, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7755110B2 | Architecture of function blocks and wirings in a structured ASIC and configurable driver cell of a logic cell zone | Electricity | 131 | Active |
| US7492187B2 | Circuit arrangement for supplying configuration data in FPGA devices | Electricity | 23 | Active |
| US7199618B2 | Logic circuit arrangement | Electricity | 20 | Expired |
| US7864579B2 | Integrated circuits having a controller to control a read operation and methods for operating the same | Physics | 10 | Active |
| US7348795B2 | Configurable logic component without a local configuration memory and with a parallel configuration bus | Electricity | 4 | Expired |
| US8589765B1 | Memory read-out | Physics | 3 | Active |
| US7323904B2 | Look-up table | Physics | 1 | Expired |
| US7439765B2 | Mask-programmable logic macro and method for programming a logic macro | Electricity | 0 | Active |
| US8533563B2 | Memory read-out | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.