Semiconductor memory device
US7200030B2 · kind B2 · utility
38Cited by
12References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2003 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Dec 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.