Semiconductor integrated circuit device and fabrication process thereof
US7202120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2005 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | May 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
Abstract
A semiconductor integrated circuit includes an n-channel MOS transistor and a p-channel MOS transistor formed respectively in first and second device regions of a substrate, the n-channel MOS transistor including a first gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, the p-channel MOS transistor including a second gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, wherein there is provided a stressor film on the substrate over the first and second device regions such that the stressor film covers the first gate electrode including the sidewall insulation films thereof and the second gate electrode including the sidewall insulation films thereof, wherein the stressor film has a decreased film thickness in the second device region at least in the vicinity of a base part of the second gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.