Mesa isolation technology for extremely thin silicon-on-insulator semiconductor devices
US7202123B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 2, 2004 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Jul 2, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Silicon-on-insulator (SOI) structures with silicon layers less than 20 nm in thickness are used to form extremely thin silicon-on-insulator (ETSOI) semiconductor devices. ETSOI semiconductor devices can be efficiently manufactured by mesa isolation techniques. A method of forming a plurality of semiconductor devices is provided comprising a SOI structure. The SOI structure comprises a substrate, an insulating layer overlying the substrate, and a silicon layer overlying the insulating layer, wherein the silicon layer has a thickness less than 20 nm. The silicon layer is patterned to create at least two laterally spaced apart silicon layers. A semiconductor device is formed at each of the at least two laterally spaced apart silicon layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.