Semiconductor package and its manufacturing method
US7202554B1 · kind B1 · utility
26Cited by
301References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2004 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Aug 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package comprising paddle and a plurality of leads which extend at least partially about the die paddle in spaced relation thereto. Attached to the die paddle is a semiconductor die which is electrically connected to at least some of the leads. Attached to the semiconductor die is at least one inner package. A package body encapsulates the die paddle, the leads, the semiconductor die and the inner package such that a portion of each of the leads and a portion of the inner package are exposed in the package body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.