Device and method for compensating defect in semiconductor memory
US7203107B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2005 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Dec 27, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device for compensating a semiconductor memory defect, suitable for use in a semiconductor memory, is provided. The device includes a memory array, having at least a defectless sub-memory region, the memory array being coupled to an address decoder circuit and a sensing circuit for storing data. A selection circuit is coupled to a control unit and outputs a selection signal to the control unit. A first input address buffer is coupled to the control unit and the address decoder circuit, and outputs an address signal to the address decoder circuit in response to the selection signal for selecting the defectless sub-memory region to store data. A method for compensating a semiconductor memory defect is also provided, including determining whether the memory region of the semiconductor memory has a defect; and replacing the memory region with the defectless sub-memory region to store data when the semiconductor memory is defective.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.