Sacrificial layer for protection during trench etch
US7205226B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2005 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | May 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3086
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for etching a trench is provided. The method initiates with providing a substrate having a patterned feature. The method includes alternating between deposition of a protective layer onto inner surfaces of the patterned feature and etching the trench into the substrate. The alternating may be achieved through a gas modulation technique and in one embodiment, the deposition and the etching are performed in the same chamber, i.e., the substrate does not move to a different chamber between the etch and deposition processes. The alternating is continued until the trench is completed and then the trench is filled. A semiconductor processing system is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.