Wafer level chip scale package having a gap and method for manufacturing the same
US7205660B2 · kind B2 · utility
10Cited by
0References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2005 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Jul 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.