Patent · US Expired

Integrated semiconductor memory comprising at least one word line and method

US7206238B2 · kind B2 · utility

4Cited by

5References

16Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Joerg Kliewer · Munich, DE
Herbert Benzinger · Birkenfeld, DE
Stephan Schroeder · Munich, DE
Manfred Proell · Dorfen, DE

Key dates

Filing date	Sep 1, 2005
Grant date	Apr 17, 2007
Priority date	—
Expiry date	Sep 2, 2025

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/1202
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A semiconductor memory and a test method for testing whether word line segments (12) are floating after an activation operation or a deactivation operation is disclosed. For this purpose, the charge-reversal current (I) that occurs in the event of a word line segment (12) being subjected to charge reversal or a charge quantity (Q) which is fed to the word line (12) or conducted away from the word line segment (12) as a result of this is measured. If, upon activation or deactivation of a word line segment (12), the measured charge-reversal current (I) or the corresponding charge quantity (Q) is less than a lower limit value, it is ascertained that the relevant word line segment (12) has a defective contact terminal. In this way, high-impedance or defective contact hole fillings can thereby be identified and the associated word line segments (12) can be replaced by redundant word lines.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.