Host memory interface for a parallel processor
US7206909B2 · kind B2 · utility
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7References
18Claims
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Key dates
| Filing date | Mar 20, 2003 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Mar 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4239
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the memory address. The memory interface can connect to a host configured to access data in a conventional SDRAM memory device so that the host can access data in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.