Duty cycle distortion compensation for the data output of a memory device
US7206956B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2006 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Feb 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for compensating for duty cycle distortion in an output data signal generated by a synchronous dynamic random access memory device (SDRAM) is provided. The output latch of the SDRAM is driven by an output clock signal generated by a delay lock loop (DLL). The output clock signal is phase-shifted relative to a reference clock signal received by the DLL such that the data removed from the output latch is synchronous with the reference clock signal. Further the duty cycle of the output clock signal is adjusted in a phase inverse relationship to the duty cycle distortion introduced by the output latch. As a result, the output data signal has reduced duty cycle distortion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.