Method of manufacturing a semiconductor device comprising stacked chips and a corresponding semiconductor device

US7208345B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Thorsten Meyer · Regensburg, DE
• Harry Hedler · Germering, DE

Key dates

• Filing date: May 11, 2005
• Grant date: Apr 24, 2007
• Expiry date: May 13, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/19107
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A first reconstituted wafer is formed, followed by a first redistribution layer. In parallel, a second reconstituted wafer is formed. The second reconstituted wafer is diced along a gap such that individualized embedded chips are formed having tilted sidewalls defining an angle of more than 90 degrees with respect to the active surface of the reconstituted wafer. The embedded chips are placed with the backside on an active surface of the first reconstituted wafer on the first redistribution layer. Afterwards, a second redistribution layer is formed on the active surface of the embedded chips and tilted sidewalls wherein the second redistribution layer connects contact pads of the second chips with the first redistribution layer.