Methods of fabricating high voltage devices
US7208364B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2005 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Jul 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
Abstract
Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.