Semiconductor chip capable of implementing wire bonding over active circuits
US7208837B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2005 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Apr 22, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/265
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A reinforced bonding pad structure includes a bondable metal layer defined on a stress-buffering dielectric layer, and an intermediate metal layer damascened in a first inter-metal dielectric (IMD) layer disposed under the stress-buffering dielectric layer. The intermediate metal layer is situated directly under the bondable metal layer and is electrically connected to the bondable metal layer with a plurality of via plugs integrated with the bondable metal layer. A metal frame is damascened in a second IMD layer under the first IMD layer. The metal frame is situated directly under the intermediate metal layer for counteracting mechanical stress exerted on the bondable metal layer during bonding, when the thickness of said stress-buffering dielectric layer is greater than 2000 angstroms, the damascened metal frame may be omitted. An active circuit portion including active circuit components of the integrated circuit is situated directly under the metal frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.