Single poly non-volatile memory
US7209392B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2005 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Apr 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erasable programmable non-volatile memory cell encompasses an ion well; a first select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; a first floating gate transistor having a drain, a source coupled to the drain of the first select transistor, a first floating gate channel region formed between its drain and source, and a common floating gate overlying the floating gate channel region; a second select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; and a second floating gate transistor having a drain, a source coupled to the drain of the second select transistor, a second floating gate channel region formed between its drain and source, and the common floating gate overlying the second floating gate channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.