Multiple-stage pipeline for transaction conversion
US7210018B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Apr 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1615
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple-stage pipeline for transaction conversion is disclosed. A method is disclosed that converts a transaction into a set of concurrently performable actions. In a first pipeline stage, the transaction is decoded into an internal protocol evaluation (PE) command, such as by utilizing a look-up table (LUT). In a second pipeline stage, an entry within a PE random access memory (RAM) is selected, based on the internal PE command. This may be accomplished by converting the internal PE command into a PE RAM base address and an associated qualifier thereof. In a third pipeline stage, the entry within the PE RAM is converted to the set of concurrently performable actions, such as based on the PE RAM base address and its associate qualifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.