System and method for accurate negative bias temperature instability characterization
US7212023B2 · kind B2 · utility
9Cited by
18References
8Claims
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Key dates
| Filing date | Sep 7, 2004 |
| Grant date | May 1, 2007 |
| Priority date | — |
| Expiry date | Sep 7, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2621
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.