Patent · US Expired

Interlevel dielectric layer and metal layer sealing

US7214608B2 · kind B2 · utility

3Cited by
2References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 29, 2004
Grant dateMay 8, 2007
Priority date
Expiry dateFeb 8, 2025

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/76844
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Methods for sealing an organic ILD layer and a metal layer after an etching step. The method includes etching through an ILD layer and leaving a remaining portion of an underlying metal layer cap, maintaining the device in an inert gas, and depositing at least a portion of a liner into the opening to seal the ILD layer and the metal layer. Subsequent processing may include formation of a via by etching through the portion of the liner and the remaining portion of the cap layer, and depositing a metal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.