Method for forming a barrier layer in an integrated circuit in a plasma with source and bias power frequencies applied through the workpiece
US7214619B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2005 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Apr 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76865
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A barrier layer is formed in an integrated circuit by providing a metal target near a ceiling of the chamber and a wafer support pedestal facing the target near a floor of the chamber. A process gas is introduced into the vacuum chamber. A target-sputtering plasma is maintained at the target to produce a stream of principally neutral atoms flowing from the target toward the wafer for vapor deposition. A wafer-sputtering plasma is maintained near the wafer support pedestal to produce a stream of sputtering ions toward the wafer support pedestal for re-sputtering. The sputtering ions are accelerated across a plasma sheath at the wafer in a direction normal to a surface of the wafer to render the sputter etching highly selective for horizontal surfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.