Strain-silicon CMOS with dual-stressed film
US7214629B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2004 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | May 9, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/942
Abstract
A semiconductor device has an NMOS portion and a PMOS portion. A first stress layer overlies a first channel to provide a first stress type to the channel and a first modified stress layer is formed from a portion of the first stress layer overlying a second channel. A second stress layer providing a second stress type overlies the first modified stress layer and a second modified stress layer is formed from a portion of the second stress layer overlying the first stress layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.