PMOS transistor with compressive dielectric capping layer
US7214630B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2005 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | May 6, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a plurality of PECVD dielectric sublayers and plasma-treating each sublayer. Compressive stress from the dielectric capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in the PMOS channel. To form a compressive dielectric layer, a deposition reactant mixture containing A1 atoms and A2 atoms is provided in a vacuum chamber. Element A2 is more electronegative than element A1, and A1 atoms have a positive oxidation state and A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms. A deposition plasma is generated by applying HF and LF radio-frequency power to the deposition reactant mixture, and a sublayer of compressive dielectric material is deposited. A post-treatment plasma is generated by applying HF and LF radio-frequency power to a post-treatment gas that does not contain at least one of A1 atoms and A2 atoms. Compressive stress in the dielectric sublayer is increased by treating the sublayer in the p…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.