Multi-source, multi-gate MOS transistor with a drain region that is wider than the source regions
US7214992B1 · kind B1 · utility
7Cited by
1References
10Claims
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Key dates
| Filing date | Oct 27, 2004 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Oct 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
Abstract
The drain breakdown voltage walk-in of a dual-source, dual-gate PMOS transistor is significantly reduced by utilizing source regions which have a width that is equal to or less than a width of the drain region. By utilizing source regions with widths that are equal to or less than the width of the drain region, the current density in the drain region is significantly reduced which reduces the number of hot charge carriers that are trapped at the silicon-to-silicon dioxide interface which, turn in, reduces the drain breakdown voltage walk-in rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.