Misalignment test structure and method thereof
US7217581B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2006 |
| Grant date | May 15, 2007 |
| Priority date | — |
| Expiry date | Jan 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.