System and method for accurate negative bias temperature instability characterization
US7218132B2 · kind B2 · utility
6Cited by
10References
12Claims
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Key dates
| Filing date | Nov 30, 2005 |
| Grant date | May 15, 2007 |
| Priority date | — |
| Expiry date | Nov 30, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2621
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.