Dual equalization devices for long data line pairs
US7218564B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2004 |
| Grant date | May 15, 2007 |
| Priority date | — |
| Expiry date | Jul 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An equalization circuit for a pair of resistive-capacitive data lines includes primary and secondary equalization circuits attached at both ends of the data line pair. A primary equalization circuit at one end of the data line pair receives a primary control signal, and a secondary equalization circuit at the other end of the data line pair receives a secondary control signal, which is different than the primary control signal. The equalization devices in the primary equalization circuit are attached near the read and write amplifiers and operate normally since all the information is available as to whether or not the corresponding data line pair should be equalized. The additional equalization devices in the secondary equalization circuit placed at the other end of the data line pair receive a simpler control signal that lacks the information as to whether or not any particular data line pair is being equalized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.