Method and apparatus for the protection of sensitive data within an integrated circuit
US7218567B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2005 |
| Grant date | May 15, 2007 |
| Priority date | — |
| Expiry date | Dec 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17768
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for the protection of memory within an integrated circuit (IC) are provided for various phases of operation of the IC. Various portions of sensitive data may be contained within battery backed random access memory (RAM) (310), which may then be protected using either a passive, or an active, zeroization sequence depending upon the phase of operation of the IC. In an idle state, detection circuit (324) senses a drop in battery power (VBATT) to launch active destruction of RAM (310) memory using active zeroization circuits (312 and 314). In a configuration state, detection circuit (402) or (504) senses a drop in battery power (VBATT) to launch active destruction of RAM (310) memory using active zeroization circuits (312 and 314). In an operational state, various methods may be employed to detect and counteract the unauthorized access to RAM (310).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.