Fabrication method of semiconductor integrated circuit device
US7219422B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2004 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | May 12, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49798
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.