Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer
US7220635B2 · kind B2 · utility
53Cited by
16References
20Claims
0Family size
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Key dates
| Filing date | Dec 19, 2003 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | Jul 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a sacrificial layer on the high-k gate dielectric layer. After etching the sacrificial layer, first and second spacers are formed on opposite sides of the sacrificial layer. After removing the sacrificial layer to generate a trench that is positioned between the first and second spacers, a metal layer is formed on the high-k gate dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.