Protection of active layers of memory cells during processing of other elements
US7220642B2 · kind B2 · utility
0Cited by
8References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 12, 2004 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | Nov 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A method of fabricating an electronic structure by providing a conductive layer, providing a dielectric layer over the conductive layer, providing first and second openings through the dielectric layer, providing first and second conductive bodies in the first and second openings respectively and in contact with the conductive layer, providing a memory structure over the first conductive body, providing a protective element over the memory structure, and undertaking processing on the second conductive body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.