System and method for gate formation in a semiconductor device
US7220643B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2005 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | Nov 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7624
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a memory device is provided. A memory cell stack is formed over a substrate. The memory cell stack includes a first layer formed over the substrate and a second layer formed over the first layer. A dielectric layer is formed over the first and second layers and the substrate. The dielectric layer is etched to expose at least an upper surface of the memory cell stack. The second layer is etched to recess the second layer with respect to an upper surface of the dielectric layer. A silicide region is formed on the second layer in the memory cell stack, where the silicide region in each memory cell stack is bounded by the dielectric layer extending above the upper surface of the memory cell stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.