Fabrication method for semiconductor structure in a substrate, the semiconductor structure having at least two regions that are to be patterned differently

US7220664B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Stephan Hartmann · Schwieberdingen, DE
• Dirk Offenberg · Dresden, DE
• Mirko Vogt · Dresden, DE

Key dates

• Filing date: Feb 22, 2005
• Grant date: May 22, 2007
• Expiry date: Feb 22, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/7682
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present invention provides a fabrication method for a semiconductor structure in a substrate, the semiconductor structure having at least two regions that are to be patterned differently. A fabrication of a patterned first region in the substrate, so that the semiconductor structure has a non-patterned second region and the patterned first region, is followed by a deposition of a cover layer that grows over the patterned first region, so that the cover layer above the patterned first region forms a closure, which covers over the patterned first region. This is followed by a fabrication of the patterned second region, the patterned first region remaining protected at least by the closure of the cover layer. The final step effected is a removal of the cover layer above the semiconductor structure, which now has two differently patterned regions.