Asymmetric source/drain transistor employing selective epitaxial growth (SEG) layer and method of fabricating same
US7221023B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2005 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | Apr 29, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/942
Abstract
According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.