Semiconductor memory chip

US7221615B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Paul Wallner · Prien am Chiemsee, DE
• Martin Streibl · Petershausen, DE
• Manfred Menke · Ritterhude, DE
• Yukio Fukuzo · Tokyo, JP
• Christian Sichert · Attenkirchen, DE
• Peter Gregorius · Munich, DE

Key dates

• Filing date: Oct 4, 2005
• Grant date: May 22, 2007
• Expiry date: Oct 4, 2025

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/4096
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.