Testing and repair methodology for memories having redundancy
US7222274B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2004 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | Jul 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31711
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing and repairing an integrated circuit having a total number of fuses for effecting repair of the integrated circuit. The method including: testing a memory array with a set of tests and reserving a first number of the total number of fuses for use in repairing the memory array based on results of the first set of tests; and shmoo testing the memory array by incrementing, decrementing or incrementing and decrementing values of a test parameter until a minimum or maximum value of the test parameter is reached that utilizes a second number of the total number of fuses for use in repairing the memory array to operate at the minimum or maximum value of the test parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.