Method of manufacturing semiconductor device with crack prevention ring
US7223673B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2004 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Oct 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a crack prevention ring at the exterior edge of an integrated circuit to prevent delamination and cracking during the separation of the integrated circuits into individual die. The crack prevention ring extends vertically into a semiconductor workpiece to at least a metallization layer of the integrated circuit. The crack prevention ring may be formed simultaneously with the formation of test pads of the integrated circuits. The crack prevention ring may be partially or completely filled with conductive material. An air pocket may be formed within the crack prevention ring beneath a passivation layer of the integrated circuit. The crack prevention ring may be removed during the singulation process. An optional seal ring may be formed between the crack prevention ring and the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.