Integrated circuit device having non-linear active area pillars
US7224020B2 · kind B2 · utility
46Cited by
2References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2005 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Nov 23, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/982
Abstract
An integrated circuit device having non-linear active area pillars. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a conductive layer to form a channel through the pillars. The pillars are patterned to form non-linear active area lines having angled segments. The conductive layer is patterned to form word lines that intersect the active area lines at the angled segments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.