Semiconductor device package with reduced leakage

US7224047B2 · kind B2 · utility

Assignee

• LSI · US

Inventors

• Patrick Carberry · Laurys Station, US
• Jeffery Gilbert · Schwenksville, US
• George Libricz · Bethlehem, US
• Ralph Salvatore Moyer · Shillington, US
• John W. Osenbach · Kutztown, US
• Hugo Safar · Westfield, US
• Thomas H. Shilling · Macungie, US

Key dates

• Filing date: Dec 18, 2004
• Grant date: May 29, 2007
• Expiry date: Dec 18, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/19041
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewalls interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.