Integrated circuit with protective moat
US7224060B2 · kind B2 · utility
14Cited by
2References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2004 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Sep 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.