Method and system for coding test pattern for scan design

US7225376B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Joerg G. Appinger · Aidlingen, DE
• Michael Kessler · Herrenberg, DE
• Manfred Schmidt · Krefeld, DE

Key dates

• Filing date: Jul 30, 2003
• Grant date: May 29, 2007
• Expiry date: Nov 25, 2024

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318566
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method and system for efficiently coding test pattern for ICs in scan design and build-in linear feedback shift register (LFSR) for pseudo-random pattern generation. In an initialization procedure, a novel LFSR logic model is generated and integrated into the system for test data generation and test vector compression. In a test data generation procedure, test vectors are specified and compressed using the LFSR logic model. Every single one of the test vectors is compressed independently from the others. The result, however, may be presented all at once and subsequently provided to the user or another system for further processing or implementing in an integrated circuit to be tested. According to the present invention a test vector containing 0/1-values for, e.g., up to 500.000 shift registers and having, e.g., about 50 so called care-bits can be compressed to a compact pattern code of the number of care-bits, i.e., 50 bits for the example of 50 care-bits.