Method of forming a dual damascene structure utilizing a three layer hard mask structure
US7226853B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2002 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Mar 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76835
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a dual damascene structure on a substrate having a dielectric layer already formed thereon. In one embodiment the method includes depositing a first hard mask layer over the dielectric layer; depositing a second hard mask layer on the first hard mask layer; depositing a third hard mask layer on the second hard mask layer and completing formation of the dual damascene structure by etching a metal wiring pattern and a via pattern in the dielectric layer and filling the etched metal wiring pattern and via pattern with a conductive material. In one particular embodiment the second hard mask layer is an amorphous carbon layer and the third hard mask layer is a silicon-containing material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.