Nano-electrode-array for integrated circuit interconnects
US7226856B1 · kind B1 · utility
19Cited by
7References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2004 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Apr 27, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/723
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and a method of manufacturing an integrated circuit is provided including providing an integrated circuit having a trench and via provided in a dielectric layer. A nano-electrode-array is formed over the dielectric layer in the trench and via, and a conductor is deposited over the nano-electrode-array. The conductor and the nano-electrode-array are coplanar with a surface of the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.