Small area contact region, high efficiency phase change memory cell and fabrication method thereof
US7227171B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 5, 2002 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Jul 17, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/947
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A contact structure, including a first conducting region having a first thin portion with a first sublithographic dimension in a first direction; a second conducting region having a second thin portion with a second sublithographic dimension in a second direction transverse to said first direction; the first and second thin portions being in direct electrical contact and defining a contact area having a sublithographic extension. The thin portions are obtained using deposition instead of lithography: the first thin portion is deposed on a wall of an opening in a first dielectric layer; the second thin portion is obtained by deposing a sacrificial region on vertical wall of a first delimitation layer, deposing a second delimitation layer on the free side of the sacrificial region, removing the sacrificial region to form a sublithographic opening that is used to etch a mold opening in a mold layer and filling the mold opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.