Wiring structure for a pad section in a semiconductor device
US7227269B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 16, 2005 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Aug 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The wiring structure of a pad section in a semiconductor device includes a row of pads and a plurality of first bias wirings provided at either side of the row of pads on a same plane. The first bias wirings carry electrical signals to the pads. A plurality of second bias wirings is formed below the layer having the first bias wirings and the pads. The second bias wirings include a set of wiring parts that run in the direction of the row of pads to overlap with adjacent pads in the layer above. The second bias wirings also include a set of wiring parts that run perpendicular to the direction of the first bias wirings and between two adjacent pads in the layer above.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.