Device for ESD protection of an integrated circuit
US7227730B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2005 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | May 31, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/911
Abstract
A device for ESD (electrostatic discharge) protection of a circuit of a semiconductor device comprises a field effect transistor based varistor with gate, source and drain regions, wherein one of the source and drain regions is connected to an input/output pad of the semiconductor device, and the other one of the source and drain regions is connected to an input/output terminal of the circuit. A biasing circuit is connected to the gate region of the varistor to create an accumulation region below the gate of the varistor at normal operating voltages of said semiconductor device. The semiconductor device is preferably an integrated device on a single substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.