Processor, data processing system and method for synchronizing access to data in shared memory
US7228385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2004 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Oct 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to determine a store target address, a store queue that, following execution of the store-conditional instruction, buffers a corresponding store operation, sequencer logic associated with the store queue. The sequencer logic, responsive to receipt of a latency indication indicating that resolution of the store-conditional operation as passing or failing is subject to significant latency, invalidates, prior to resolution of the store-conditional operation, a cache line in the store-through upper level cache to which a load-reserve operation previously bound.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.