Method for handling 32 bit results for an out-of-order processor with a 64 bit architecture

US7228403B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Petra Leber · Ehningen, DE
• Jens Leenstra · Nagold, DE
• Wolfram Sauer · Herrenberg, DE
• Dieter Wendel · Schenefeld, DE

Key dates

• Filing date: Dec 18, 2001
• Grant date: Jun 5, 2007
• Expiry date: Nov 6, 2024

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/3858
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method for operating a processor having an architecture of a larger bitlength with a program comprising instructions compiled to produce instruction results of at least one smaller bitlength having the steps of detecting when in program order a first smaller bitlength instruction is to be dispatched which does not have a target register address as one of its sources, and adding a so_extract_instruction into an instruction stream before the smaller bitlength instruction. The extract instruction includes the steps of dispatching the extract instruction together with the following smaller bitlength instruction from an instruction queue into a Reservation Station, issuing the extract instruction to an Instruction Execution Unit (IEU) as soon as all source operand data is available and an IEU is available according to respective issue scheme, executing the extract instruction by an available IEU, setting an indication that the result of the instruction needs to be written into the result field of the instruction following the extract instruction, and writing the extract instruction result into the result field of the first instruction, and into all fields of operands being dependent o…